Parallel correlated double sampling technique for pipelined analogue-to-digital converters

Introduction: In a switch-capacitor realisation of the multiplying digitalto-analogue converter (MDAC) used in algorithmic and pipeline analogue-to-digital converters (ADCs), the settling behaviour of the opamp determines the speed and accuracy of the ADC. Fast settling requires high unity gain bandwidth, while accurate settling requires a high DC gain. As gate lengths continue to shorten, high gain opamp design becomes complex and thus limits the speed of the ADC. One way of overcoming this limitation is by designing a low-gain, high-speed opamp and using correlated double sampling (CDS) to double the effective gain (in dB) [1]. However, the CDS technique increases the kT=C noise power of the ADC [2], requiring larger capacitance values. The proposed MDAC structure allows use of a low-gain opamp to achieve high settling accuracy without the noise penalty.